/usr/man/cat.3/OPENSSL_ia32cap_loc.3(/usr/man/cat.3/OPENSSL_ia32cap_loc.3)

OPENSSL_ia32cap(3)           OpenSSL           OPENSSL_ia32cap(3)

NAME

     OPENSSL_ia32cap, OPENSSL_ia32cap_loc - the IA-32 processor
     capabilities vector

SYNOPSIS

      unsigned long *OPENSSL_ia32cap_loc(void);
      #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])

DESCRIPTION

     Value returned by OPENSSL_ia32cap_loc() is address of a
     variable containing IA-32 processor capabilities bit vector
     as it appears in EDX:ECX register pair after executing CPUID
     instruction with EAX=1 input value (see Intel Application
     Note #241618). Naturally it's meaningful on x86 and x86_64
     platforms only. The variable is normally set up
     automatically upon toolkit initialization, but can be
     manipulated afterwards to modify crypto library behaviour.
     For the moment of this writing following bits are
     significant:

     bit #4 denoting presence of Time-Stamp Counter.
     bit #19 denoting availability of CLFLUSH instruction;
paths;
     bit #20, reserved by Intel, is used to choose among RC4 code
     bit #23 denoting MMX support;
     bit #24, FXSR bit, denoting availability of XMM registers;
     bit #25 denoting SSE support;
     bit #26 denoting SSE2 support;
cores with shared cache;
     bit #28 denoting Hyperthreading, which is used to distinguish
     bit #30, reserved by Intel, denotes specifically Intel CPUs;
     bit #33 denoting availability of PCLMULQDQ instruction;
     bit #41 denoting SSSE3, Supplemental SSE3, support;
CPUs);
     bit #43 denoting AMD XOP support (forced to zero on non-AMD
     bit #57 denoting AES-NI instruction set extension;
     bit #59, OSXSAVE bit, denoting availability of YMM registers;
     bit #60 denoting AVX extension;
     bit #62 denoting availability of RDRAND instruction;

     For example, clearing bit #26 at run-time disables high-
     performance SSE2 code present in the crypto library, while
     clearing bit #24 disables SSE2 code operating on 128-bit XMM
     register bank. You might have to do the latter if target
     OpenSSL application is executed on SSE2 capable CPU, but
     under control of OS that does not enable XMM registers. Even
     though you can manipulate the value programmatically, you
     most likely will find it more appropriate to set up an
     environment variable with the same name prior starting
     target application, e.g. on Intel P4 processor 'env
     OPENSSL_ia32cap=0x16980010 apps/openssl', or better yet 'env
     OPENSSL_ia32cap=~0x1000000 apps/openssl' to achieve same

1.0.2t               Last change: 2019-09-10                    1

OPENSSL_ia32cap(3)           OpenSSL           OPENSSL_ia32cap(3)

     effect without modifying the application source code.
     Alternatively you can reconfigure the toolkit with no-sse2
     option and recompile.

     Less intuitive is clearing bit #28. The truth is that it's
     not copied from CPUID output verbatim, but is adjusted to
     reflect whether or not the data cache is actually shared
     between logical cores. This in turn affects the decision on
     whether or not expensive countermeasures against cache-
     timing attacks are applied, most notably in AES assembler
     module.

     The vector is further extended with EBX value returned by
     CPUID with EAX=7 and ECX=0 as input. Following bits are
     significant:

     bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
     bit #64+5 denoting availability of AVX2 instructions;
and RORX;
     bit #64+8 denoting availability of BMI2 instructions, e.g. MUXL
     bit #64+18 denoting availability of RDSEED instruction;
     bit #64+19 denoting availability of ADCX and ADOX instructions;

1.0.2t               Last change: 2019-09-10                    2

See also OPENSSL_ia32cap(3)